The continuing demand for higher speed and lower cost semiconductor memories has led to the development of the virtual ground configuration for read-only type memories. Virtual ground memories are a well-known technique for increasing the array density while at the same time maintaining process compatibility with existing double-level polysilicon n-channel processes. Representative examples of virtual ground memory arrays are disclosed in U.S. Pat. Nos. 3,916,169; 3,934,233; 4,021,781 and 4,387,447. A process for fabricating contactless electrically programmable and electrically erasable memory cells (EPROMs) of the flash variety for use in a virtual ground array is disclosed in U.S. Pat. No. 4,780,424 of Holler et al., which is assigned to the assignee of the present application. The contactless cells of Holler et al., use elongated source and drain regions disposed beneath field oxide regions. The drain regions are shallow compared to the source regions, while the source regions are characterized more by a graded junction.
While virtual ground memories do enjoy an advantage from the perspective of increased bit density, they are not without their disadvantages. One possible drawback of a contactless EPROM array and of virtual ground memory arrays in general, is the problem of unwanted interaction between adjacent cells. This interference is usually manifested as a program disturb condition, (i.e., unwanted programming of an unselected adjacent cell), or as read access degradation due to an unwanted current component. In both situations the interference is to the electrically programmable read-only memory cell located in the adjacent column and connected to the selected word line. Interaction between adjacent cells also leads to the formation of parasitic currents which interfere with reading, erasing and programming of individual cells. Ultimately, the access speed and the integrity of the memory array is adversely affected by these problems.
To overcome the drawbacks associated with prior art virtual ground architectures, the present invention provides an apparatus and method for eliminating parasitic currents during read mode operations in a virtual ground EPROM memory array. Importantly, the present invention achieves this result without sacrificing data access speed. The invention utilizes an additional voltage source to establish a read bias potential along the adjacent bit line (adjacent to the cell selected). This effectively shields possible interference from adjacent columns and speeds up the charging or discharging of the selected column.
Additionally, the present invention employes a debiasing scheme which uses intercolumn pass gates along with a slow ramping of the selected column voltage to avoid disturbance of adjacent cells during programming.